In semiconductor wafer fabrication, the component features of the integrated circuits (ICs) are defined on the wafer using well known patterning and etching techniques. Traditionally, a layer of photoresist material is deposited onto a wafer. The wafer typically has a substrate layer or layers, and various overlying intermediate layers formed of either conductive materials or dielectric materials, depending upon the type of device being fabricated. The photoresist material is then patterned by photolithography techniques, e.g., exposing the photoresist to electromagnetic radiation (light) filtered by a reticle. After passing through the reticle, the light impinges upon the surface of the photoresist material. The light alters the chemical composition of the photoresist material such that a developer can be used to remove either the exposed regions, or the unexposed regions, depending upon whether positive or negative photoresist materials were employed. Positive photoresist is predominantly used in current generation sub-micron feature fabrication. With positive photoresist materials, the light alters the structure and chemical properties of the photoresist, and converts exposed regions to base-soluble polymer fragments through the photogeneration of acid species. These base-soluble sections are removed using a solvent in a development process, which leaves a number of photoresist lines remaining. Then the wafer is etched to remove the material from areas not protected by the photoresist material, thus defining the desired features of the wafer.
As the density of integrated circuits (ICs) increases, feature sizes of the lines and components in the ICs correspondingly decreases. Even with the numerous enhancements of photolithography systems to realize these decreasing feature sizes, current lithographic systems cannot define features much under about 0.13 microns. This limitation is due to several factors such as reticle/mask pattern fidelity, optical proximity effects, and diffusion and loading effects during resist and etch processing. Various techniques have been devised in attempts to reduce feature sizes within the framework of current lithographic systems. One such technique, called photoresist trimming, utilizes dry plasma etching as a method for further reducing the critical dimension (CD) of features, e.g., gates, via resist etching by neutral and ion species generated in the plasma.
There are various types of dry plasma reactors known in the art of advanced wafer fabrication, for example, downstream etch systems, decoupled plasma source (DPS), reactive ion etch (RIE), electron-cyclotron resonance (ECR), inductively-coupled plasma (ICP), and magnetically enhanced RIE (MERIE), to name a few. The principal dry etch applications are etching of dielectric, etching of silicon, and etching of metal. Generally, well controlled etch profile and CD uniformity are achieved with these various plasma systems. The primary disadvantage to these dry etch processes is their poor selectivity to the underlying layer, which requires frequent monitoring during etch to minimize over-etching into the underlying layers.
Current resist trimming techniques to generate features of smaller CD than can be achieved through photolithographic techniques alone achieve the target CD by trimming for an interval of time based on the lateral resist trim rate, which results in an open-loop control (endpoint detection is not possible). In this conventional approach, resist is trimmed laterally, and vertically, for a required time interval, tTRIM, based upon an empirically derived horizontal trim rate RH, typically in nm per second (nm/s). However, if etch chamber conditions change, as they are prone to do, the empirically derived trim rate may change such that the etch rate increases or decreases during the required etch time interval, resulting in under-etch or over-etch of the CD.
Optical emission spectroscopy (OES), which is based upon changes in the spectrum of radiation emitted by the plasma during etch, is one commonly used monitoring technique in dry etching processes. While OES can help detect the onset of complete removal of the current etched layer in a stack, OES cannot supply information about etch rate or relative thickness, nor can it be applied for endpoint detection in resist trim processes if the material layer underlying the feature undergoing etch interacts continuously with the plasma (is not etched away) during the etch process. This is because there is no change in species during the process for the OES to detect to determine an endpoint, and thus an open-loop (time dependent) control process is required to achieve the proper CD of the desired feature. This concept is illustrated in FIGS. 1 and 2.
FIG. 1 shows a cross-sectional view of a portion of a semiconductor device 100 about to undergo a resist trim (dry etch process) to alter the CD of the desired defining feature. The semiconductor device portion 100 has already been subjected to photo patterning as previously discussed, with the defining feature 14 in the example being a photoresist mask structure used to pattern a subsequent feature, such as a gate. Semiconductor device portion 100 consists of a substrate 9, formed of, e.g., silicon, a first layer 10 formed of, e.g., poly silicon, formed over substrate 9, and a dielectric ARC (anti-reflective layer) layer 12, formed of, e.g., silicon nitride, formed over poly silicon layer 10, and a photoresist defining feature 14 having an initial width 5. For simplicity of illustration, semiconductor device portion 100 is shown comprising only three layers, but as is well known in the art, more layers may be provided.
FIG. 2 shows a prior art result of resist trimming on semiconductor device portion 100 after completion of resist trimming. During trim, the dielectric ARC layer 12 interacts continuously with the plasma, however dielectric ARC layer 12 is not etched away at a significant rate. Thus dielectric ARC layer 12 is unchanged in vertical dimension (thickness), and there is no new species generated for OES endpoint detection. Defining feature 14 has been trimmed laterally (and vertically) during the process, based upon an empirically determined lateral trim rate for the plasma chamber RH, typically in units of nm/sec, according to the following formula:WFINAL=WINITIAL−RH×tTRIM 
Where WFINAL is the final width 7 of the critical dimension of defining feature 14, WINITIAL is the initial width 5 of the defining feature 14, RH is the lateral trim rate, and tTRIM is the amount of time required for trimming to achieve the CD final width 7. Depending upon chamber conditions during a resist trim process, final width 7 of defining feature 14 may or may not be the desired CD, as previously discussed, necessitating an open loop control.
Optical interferometry (broadband or laser source) is an additional monitoring technique used with dry etching tools. Optical interferometry is based upon detection of the optical characteristics of a broadband or laser source reflected from the etched surface. Unlike OES, interferometry provides both etch rate and thickness, but is more sensitive to the optical and geometrical properties of the material. Optical interferometry may be successfully used, for example, in the monitoring of poly silicon etching of the gate stack. As the poly silicon is etched away, the stack becomes more transparent and the resultant interference between patterned and open areas results in interference fringes of increasing amplitude. It is straightforward in this case to determine the extent of poly silicon remaining and determine endpoint. However, when optical interferometry is used during resist trim, the thickness of the etched resist does not change as significantly, and a large dependency exists on the exact pattern density of the location being monitored. Hence, optical interferometry monitoring techniques are not generally suitable for resist trim endpoint monitoring on a conventional stack.
Therefore, what is needed is a reliable method for photoresist endpoint detection that maintains a consistent critical dimension and provides for a closed loop process.